1. Field of the Invention
The present invention relates generally to circuits for transforming a first signal varying between a low voltage and a high voltage into a second signal varying between a lower voltage and a higher voltage, the lower voltage being smaller than the low voltage and/or the higher voltage being greater than the high voltage.
2. Discussion of the Related Art
Such circuits are for example used as interface circuits between circuits operating with different supply voltages. The circuits may belong to a same integrated circuit supplied between a higher voltage Vdd and a lower voltage Gnd, for example, 1.2V and 0V for a so-called “0.12-μm” CMOS technology. One of the circuits, for example, a memory, is supplied between a voltage Vmin, for example, 0.4V, and a voltage Vmax, for example, 0.8V, and provides signals varying between voltages Vmin and Vmax. Voltages Vmin and Vmax may be generated from voltage Vdd by DC/DC voltage converters. To make the signals originating from the memory compatible with the rest of the integrated circuit, an interface circuit transforms the signals varying between voltages Vmin and Vmax into signals varying between voltages Gnd and Vdd.
A known interface circuit of very simple design is an inverter transforming a first signal varying between 0.4V and 0.8V into a second signal varying between 0V and 1.2V. The inverter is for example formed of a PMOS transistor and of an NMOS transistor having their sources respectively connected to voltages 1.2V and 0V. The transistor gates receive the first signal. The transistor drains are connected to the output of the inverter providing the second signal. Whatever the voltage value of the first signal, the NMOS and PMOS transistors are always conductive since their gate-source voltage is greater than a threshold voltage, which is approximately 0.4V for the “0.12-μm” technology. Thus, in the described interface circuit, the inverter permanently exhibits a consumption of power. Further, the output levels are not exactly equal to 0V and 1.2V.
FIG. 1 shows another interface circuit known as a “Schmitt trigger”. The source of PMOS transistor 1 is connected to voltage Vdd, its drain is connected to the source of a PMOS transistor 2 having its drain connected to output S1 of the Schmitt trigger. The source of an NMOS transistor 3 is connected to voltage Gnd, its drain is connected to the source of an NMOS transistor 4 having its drain connected to output S1. The gates of transistors 1, 2, 3, and 4 receive on input E1 of the Schmitt trigger a first signal varying between 0.4V and 0.8V. The gate of a PMOS transistor 5 is connected to output S1, its drain is connected to voltage Gnd and its source is connected to the drain of PMOS transistor 1. The gate of an NMOS transistor 6 is connected to output S1, its drain is connected to voltage Vdd and its source is connected to the drain of NMOS transistor 3.
The Schmitt trigger provides on its output S1 a second signal which takes value 0V when the first signal increases and exceeds a first switching threshold, for example, 0.7V, and which takes value 1.2V when the first signal decreases and falls under a second switching threshold, for example, 0.5V. When the first signal is 0.4V, PMOS transistors 1 and 5 are conductive. When the first signal is 0.8V, transistors 3 and 6 are conductive. Accordingly, the Schmitt trigger exhibits a high static power consumption.
Thus, a common disadvantage of the two previously-described interface circuits is that their static power consumption is high.